Methods of fabricating crystalline silicon, thin film transistors, and solar cells

ABSTRACT

The present invention includes methods to crystallize amorphous silicon. A structure including a conductive film with at least one conductive layer in thermal contact with an amorphous silicon (a-Si) layer to be crystallized is exposed to an alternating or varying magnetic field. The conductive film is more easily heated by the alternative or varying magnetic field, which, in-turn, heats the a-Si film and crystallizes it while keeping the substrate at a low enough temperature to avoid damage to or bending of the substrate. The method can be applied to the fabrication of many semiconductor devices, including thin film transistors and solar cells.

REFERENCE TO RELATED APPLICATIONS

This application claims one or more inventions which were disclosed inProvisional Application No. 60/935,332, filed Aug. 8, 2007, entitled“METHODS OF FABRICATING CRYSTALLINE SILICON FILMS, THIN FILMTRANSISTORS, AND SOLAR CELLS”. The benefit under 35 USC §119(e) of theUnited States provisional application is hereby claimed, and theaforementioned application is hereby incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention pertains to the field of semiconductor fabrication. Moreparticularly, the invention pertains to methods of crystallizingamorphous silicon film and methods of forming thin film devicestructures such as thin film transistors and thin film solar cellsincorporating the silicon film formed using such crystallizationprocess.

2. Description of Related Art

Polycrystalline silicon (polysilicon) thin films are used in devicessuch as thin film transistors (TFTs) or solar cells. The polysilicon TFTarrays are used as backplanes for switching liquid crystal displays(LCDs) and for driving organic light emitting diode (OLED) displays. Forthe LCD applications, polycrystalline TFTs are used instead of morepopular amorphous silicon (a-Si) TFTs when the peripheral drivingcircuit is also made using TFTs, since polysilicon TFTs have about twoorders of magnitude higher carrier mobility compared to a-Si TFTs.Additionally, for higher resolutions LCDs, polysilicon TFTs arepreferred over a-Si TFTs. For OLED applications, currently the use ofpolysilicon TFTs is the only practical way to make reliable displays, asinstability of a-Si TFTs makes long term OLED operation difficult.

In polysilicon TFTs, the active layer (channel of TFT) is made ofpolycrystalline silicon. During the fabrication of polysilicon TFTs, thechannel layer is usually deposited as a-Si and then it is subsequentlyannealed to convert it to polycrystalline silicon. This process isreferred to as crystallization. The crystallization of a-Si needs to beperformed at a thermal budget (temperature/time budget) lower than thatwhich can damage the glass substrate used for the display. The mostcommonly used method for crystallization in the industry today isexcimer laser annealing (ELA), as thermal budgets encountered during theELA do not cause damage the glass substrate. Although the ELA process isthe most commonly used method, it has several disadvantages. First ofall, the ELA process is expensive in terms of cost of equipment, itsoperation and maintenance. Secondly, since the ELA is performed byscanning a pulsed laser beam, there is a non-uniformity in TFTcharacteristics resulting from pulse to pulse variation of the laserbeam. The scanning non-uniformity is visible on an image of an OLEDdisplay in the form of scan lines. Additionally, there is a high surfaceroughness for the polycrystalline silicon layer formed using ELA. Laserannealing is not suitable for creating thicker polycrystalline films(several thousand angstroms to several micrometers) that are needed insolar cells, because laser annealing does not efficiently produce thesefilms.

The least expensive and simplest crystallization process for a-Si isthermal annealing and it is known as solid phase crystallization (SPC).However, the thermal budgets needed to crystallize a-Si by SPC are toohigh to be practical for mass production of TFTs. For example, for a-Sifilms deposited at about 250° C. by a PECVD method, the annealing timeneeded to crystallize the films at 600° C. is about 15 hours. Such timesare too long for mass production of devices.

The annealing times for crystallization can be reduced exponentially byincreasing the temperature. For example, for the same a-Si filmmentioned above, the crystallization time at 650° C. is about 80 minutesand, at 700° C., it is of the order of 10 minutes. However, the glasssubstrate used for these TFTs can easily bend at these thermal budgets.

In order to reduce the thermal budget for crystallization of a-Si,people have deposited very thin (10-30 angstrom) Ni or Pd films on thea-Si surface and crystallized it by a process called metal inducedcrystallization (MIC) at a thermal budget 100 to 150° C. lower thanthose needed during SPC. The crystallization in this case proceeds byformation of a crystalline silicide (example Nickel silicide). Thismethod is very attractive because of its lower thermal budget, butduring the annealing, there is an incorporation of the metals and/ortheir silicides into the entire silicon layer, which affects the devicecharacteristics adversely, especially the leakage current, whichincreases significantly for these devices.

The amorphous silicon film deposited on a substrate such as glass can beselectively heated by generating an alternating or varying magneticfield by introducing alternating electrical current in an induction coilin the vicinity of the amorphous silicon film (U.S. Pat. No. 6,747,254,issued Jun. 8, 2004, entitled “Apparatuses for heat-treatment ofsemiconductor films under low temperature”, incorporated herein byreference). This is done to keep the substrate at a temperature lowerthan the a-Si crystallization temperature, while the a-Si film is at ahigh enough temperature to crystallize. However, heating of the film dueto the magnetic field strongly depends upon the conductivity of thefilm. Since the conductivity of amorphous silicon is very low (could beas low as 10⁻¹² S/cm), the magnetic field is unable to effectively heatthe a-Si film. Alternatively, a conductive susceptor can be placed underthe substrate and heated by the magnetic field, but this has adisadvantage of the substrate being heated by the susceptor.

SUMMARY OF THE INVENTION

The present invention includes a method to crystallize amorphous siliconfilm on a substrate by selectively heating it at a temperature higherthan the substrate. A structure includes a conductive film made up ofone or more layers in thermal contact with an amorphous silicon (a-Si)film. The conductive film is inductively heated by an alternating orvarying magnetic field. The conductive film has a higher conductivitythan the a-Si film, thus the conductive film is more easily heated bythe alternative or varying magnetic field. The heated conductive filmin-turn heats the a-Si film and crystallizes it while keeping thesubstrate at a low enough temperature to avoid damage to or bending ofthe substrate. The conductive film may be in direct contact with thea-Si film or may be separated by a thin intermediate layer that easilyallows heat transfer from the conductive film to the a-Si film. In oneembodiment, the method is applied to the fabrication of thin filmtransistors or solar cells.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A shows a structure to crystallize amorphous silicon in anembodiment of the present invention.

FIG. 1B shows another structure to crystallize amorphous silicon in anembodiment of the present invention.

FIG. 1C shows another structure to crystallize amorphous silicon in anembodiment of the present invention.

FIG. 1D shows another structure to crystallize amorphous silicon in anembodiment of the present invention.

FIG. 2 is a schematic of a inverted-staggered (bottom-gate) TFTstructure fabricated with the silicon channel layer crystallizedaccording to a method of the present invention.

FIG. 3A shows a structure early in the fabrication process of atop-gate, co-planar TFT structure incorporating the silicon channellayer crystallized by a method of the present invention.

FIG. 3B depicts another structure during the fabrication process of atop-gate, co-planar TFT structure incorporating the silicon channellayer crystallized according to a method of the present invention.

FIG. 4A shows a schematic for crystallization of a-Si by lateral growthby dividing a long channel into multiple short channels.

FIG. 4B show another schematic for crystallization of a-Si by lateralgrowth by dividing a long channel into multiple short channels.

FIG. 4C show another schematic for crystallization of a-Si by lateralgrowth for application to short channel devices.

FIG. 4D shows another schematic for crystallization of a-Si by lateralgrowth by dividing a long channel into multiple short channels.

FIG. 5A show a schematic for crystallization of a-Si by lateral growthby dividing a long channel into multiple short channels.

FIG. 5B show another schematic for crystallization of a-Si by lateralgrowth by dividing a long channel into multiple short channels.

FIG. 5C show another schematic for crystallization of a-Si by a lateralgrowth by dividing a long channel into multiple short channels.

FIG. 6 shows a schematic of a solar cell structure with at least onesilicon layer crystallized according to a method of the presentinvention.

FIG. 7A shows a flow chart of an embodiment of a method of the presentinvention.

FIG. 7B shows a flow chart of another embodiment of a method of thepresent invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 7A shows a flowchart of a method of the present invention, as itmight be used to create the structure shown schematically in FIGS. 1Aand 1C. According to the method, in step 70, an a-Si film 1 (for exampleto be used as a channel layer of a TFT) of the desired thickness isdeposited on a substrate such as glass (not shown). If needed, the a-Sifilm may be lightly doped, for example, for threshold voltage adjustmentof the TFT, but the doping levels for this film would be very low(generally of the order of 10¹⁷ cm⁻³). Thus, this film can be referredto as an undoped a-Si film or just an a-Si film. In step 71, aconductive film 2 is deposited on the a-Si film (FIG. 1A.) In step 72, amagnetic field is generated by passing current or varying current in aninduction coil placed in the vicinity of the structure. The magneticfield is preferably an alternative magnetic field or a varying magneticfield. This will raise the temperature of the conductive film byinduction heating. The power imparted by the magnetic field increaseswith the conductivity, thus a higher power would be imparted to theconductive film compared to lower conductivity films such as the a-Sifilms. This will cause the conductive film to heat up to a highertemperature. The heat will be transferred from the conductive film tothe a-Si film, leading to crystallization of the a-Si film. The glasssubstrate can be kept at a lower temperature as its conductivity is verylow.

Some embodiments of the present invention use an intermediate layer 2Abetween the conductive film and the a-Si film as shown in FIGS. 1C and1D. Some reasons to include an intermediate layer 2A include, but arenot limited to, to protect the amorphous silicon from environmentalimpurities or from environmental reaction, to prevent impurities fromthe conductive film 2 from entering into the silicon film 1, or to stopa possible reaction between the conductive film 2 and the a-Si film 1.The intermediate layer could be a part of device structure such as agate insulator layer (for example, a silicon oxide layer or a siliconnitride layer) in a thin film transistor structure or it could be anadditional layer, which may be removed later if not necessary for thefinal structure. In other embodiments, a barrier layer (not shown) maybe in between the substrate and the a-Si film 1 to minimize thecontamination from the substrate into the a-Si film 1 and also toincrease the temperature difference between the a-Si film 1 and thesubstrate to further minimize the bending or deformation of thesubstrate.

During the above mentioned crystallization process, the substrate canalso be heated with a heating apparatus including, but not limited to, aresistance-heated furnace or one or more lamps to aid thecrystallization process. In this case, the temperature of the substratecan be controlled such that the temperature does not get high enough tocause the substrate to substantially bend or become otherwise damaged.

The conductive film can be located above, below or both above and belowthe a-Si film. In the case where the conductive film is located belowthe a-Si film, as shown in the flow chart in FIG. 7B and schematicallyshown in FIGS. 1B and 1D, first a conductive film 2 is deposited in step73. Subsequently, an amorphous silicon film 1 is deposited in step 74.Then, the magnetic field crystallization is carried out as describedabove (step 75). If needed, an intermediate film 2A can be depositedbetween the a-Si film and the conductive film, as shown in FIG. 1D.

The conductive film may be a film including, but not limited to, acarbon film, graphite film, a doped a-Si or doped microcrystallinesilicon film, transparent conductor films such as ITO or IZO or a stackof two or more of these films. The conductive film may contain Fe. Theconductive film may be a magnetic film. A metal film may be used as theconductive film in direct contact with the a-Si film if it does notreact with the a-Si film or cause any impurities to be incorporated intothe a-Si that can cause undesirable deterioration of the properties ofthe crystallized film or deterioration in the characteristics of thedevice fabricated using the crystallized film. A metal layer can be usedas the conductive film if an intermediate layer is kept between the a-Silayer and the conductive film. When a doped film is used as theconductive film, the dopants are preferably from group III or group Velements of the periodic table. Since heavily doped a-Si films can bemore easily crystallized compared to undoped a-Si films, the doped filmnot only provides heat to the undoped film during the crystallizationprocess, but also acts as a crystallization seed for the a-Si film incontact with it, since the crystal seeds will first begin to form in thedoped silicon film. This is advantages since a doped silicon film notonly heats provides the heat, but also speeds up the crystallizationprocess by facilitating seeding or nucleation process of a-Sicrystallization. This seeding process also improves the crystallinequality of the resulting crystallized film. When a doped a-Si film isused as the conductive film, the preferred conductivity value for thedoped film is 10⁻³ S/cm or higher.

After the crystallization of the a-Si film is carried out, theconductive film can be removed completely. Alternatively, the conductivefilm may be removed selectively from some parts or it can be left in thedevice as a device application requires. When an intermediate layer ispresent in the structure, the intermediate layer may similarly beremoved completely, removed selectively, or remain on the structure. Forthe sake of convenience, this process will be referred to as magneticfield crystallization herein.

When a doped silicon film is used as the conductive film, the doped filmmay be produced by incorporating dopant atoms into silicon during thedeposition (gas phase doping) or it may be formed on top of the a-Sifilm (to be crystallized) by implanting dopant atoms in a-Si. Generallyfor the doped film case, the dopant concentration needs to be higherthan 10¹⁸ cm⁻³. Preferably, the dopant concentration is higher than 10²⁰cm⁻³. When the doped a-Si conductive film is in direct contact with thea-Si film, it can also act as a crystallization seed as it cancrystallize faster. In this case, a boron doped a-Si film is preferredas it crystallizes faster than other a-Si films doped with otherdopants.

The thickness of the conductive film is preferably from about 50angstroms to several thousand angstroms. The intermediate layer ispreferably several 10s of angstroms to several 1000s of angstroms thick.The heat transfer from the conductive film to the a-Si film would dependupon the thickness and thermal conductivity of the intermediate layer,with a thinner film and/or a film a higher thermal conductivity beingpreferred for efficient heat transfer.

The crystallization times for the methods of the present inventiondepend upon the thickness of the undoped a-Si film (to be crystallized),with thicker films requiring correspondingly longer times. Also, thethickness and conductivity of the conductive film would affect thecrystallization time, with a higher value of either thickness orconductivity leading to a reduction in crystallization time of the a-Sifilm.

When a doped silicon film is used as a conducting layer, it can beetched away after the crystallization. The doped film can be etched awayentirely from the top of the undoped a-Si film or it can be selectivelyetched. For example, it can be etched away only over the channel regionwhile leaving it in source-drain areas for making contacts to TFTs. Ifthe doped layer is entirely etched, either p-channel or n-channel TFTscan be formed by p-type or n-type doping of the source-drain regions ofTFTs, respectively. If the doped layer is kept in the source and drainareas, only one type of TFT can be fabricated consistent with theconductivity type of the doped layer. The latter is a simpler process asadditional steps for doping source-drain regions are not needed.

The crystallization thermal budgets can be further reduced if theproposed crystallization process is performed in an oxidizing ambient.O₂ or H₂O ambient may be used as the oxidizing ambient. At higherpressures, the oxidation rates are faster, thus crystallization thermalbudgets can be even further reduced if high pressures are used incombination with an oxidizing ambient.

TFT APPLICATION EXAMPLE 1 Inverted Staggered TFT STructure

This example applies the crystallization methods of the presentinvention to a bottom-gate type TFT.

As shown in FIG. 2, a gate-electrode layer 3 is deposited and patternedon a substrate 4. The substrate 4 may optionally have a barrier layer(not shown) on top of it. A gate-insulator layer 5 is deposited on thegate-electrode layer 3. Materials to use for the gate-insulator layerinclude, but are not limited to, silicon dioxide, silicon nitride or astack of silicon dioxide and silicon nitride layers or any otherinsulating material. On the gate insulator layer 5, an undoped amorphoussilicon layer 6 is deposited on the gate-insulator layer 5 withoutbreaking the vacuum. The undoped amorphous silicon layer 6 is the activelayer or channel layer to be crystallized. Magnetic fieldcrystallization can be carried out at this stage in fabrication, as thegate-electrode layer 3 can be efficiently heated by the magnetic field.Additionally, the substrate may optionally be heated by other means(such as furnace, or lamps) to aid the crystallization process. Insteadof employing the magnetic field crystallization of amorphous silicon atthis stage, it is also possible to employ it at a later stage in the TFTprocessing, as discussed further below.

A doped silicon layer 7, which is preferably a doped a-Si or a dopedmicrocrystalline silicon layer, is formed by deposition on the channelsilicon layer 6. A doped a-Si layer 7 is preferably formed by gas phasedoping or by ion implantation or ion doping. The doped layer 7 may beformed continuously or it can be formed discontinuously, for example,formed on source-drain areas but not on channel areas of TFTs. Thecrystallization of the a-Si layer 6 by the magnetic field may be carriedout at this stage in fabrication instead of at the earlier stagementioned above. If the crytallization is carried out at this stage, thegate-electrode layer 3, as well as the doped silicon layer 7, will helpin crystallization. The crystallization of the a-Si layer 6 is furthersped up by seeding from the doped silicon layer 7, as was discussedearlier. The doped silicon layer 7 alone can cause crystallization ofthe a-Si layer 6, if the heat-transfer from the gate electrode layer 3is not efficient due to lower thermal conductivity and/or higherthickness of the gate insulator layer 5. The gate insulator materialsused in TFTs generally have low thermal conductivities and generally arethick enough to prevent efficient heat flow from a gate electrode layerto an a-Si layer, thus application of the magnetic field crystallizationwould be beneficial if performed after deposition of a doped or aconductive layer on the a-Si layer.

The doped layer 7 and the channel silicon layers 6 are preferablypatterned simultaneously to form silicon islands to electrically isolatedevices from each other. A source drain electrode layer is deposited onthis structure. It is also possible to use the magnetic fieldcrystallization process at this stage. The source drain electrode layer,the doped silicon layer 7 and the gate-electrode layers all can beheated by the magnetic field to help crystallize the a-Si layer 6. Thesource drain electrode layer is patterned to form source and drainpatterns 8 and the source-drain electrode layer and the doped siliconlayers 7 are etched away from above the active layer 6 of the TFTs asshown in FIG. 2.

FIG. 2 shows the TFT structure fabricated using the process described sofar. One or more additional passivation layers such as silicon nitrideand/or one or more pixel electrode layers such as indium tin oxide (ITO)or indium zinc oxide (IZO) layers may be added to complete the TFTarrays. Pixel electrode layers are conductive layers and magnetic fieldcrystallization may also be carried out after deposition of a pixelelectrode layer instead of at any of the earlier stages. The pixelelectrode layer is preferably subsequently patterned. A passivationsilicon nitride layer may be used as source of hydrogen to passivate thepolysilicon grain boundaries in order to improve the performance of theTFTs.

TFT APPLICATION EXAMPLE 2 Co-Planar Structure

FIGS. 3A and 3B show a fabrication process for a top gate TFT co-planarstructure using an a-Si crystallization method of the present invention.A barrier layer 10 is deposited on a substrate 9. In one embodiment, thebarrier layer 10 is made of silicon nitride. An a-Si layer 11, undopedor lightly doped, is deposited on the barrier layer 10 as the activelayer. A conductive film 12 is deposited on the a-Si layer 11. Ifneeded, an intermediate layer (not shown in the figures) may beinterposed between the conductive film 12 and the a-Si layer 11. Theconductive film 12 may be a film including, but not limited to, agraphite film, a doped silicon film, a metal film or a magnetic film. Ifthe conductive film 12 is a doped silicon film, it may be a filmincluding, but not limited to, a doped a-Si or a doped microcrystallinesilicon film. Alternatively, the top part of the active layer 11 mayalso be doped by implanting/or diffusing dopants. Instead of placing theconductive film 12 on the top, it may alternatively be placed under thebarrier layer 10. In that case, it would be preferable that theconducting film is made of a transparent conductor to allow the displaylight to pass through it. In that embodiment, an additional heat sink orthermally insulating layer between the substrate 9 and the conductivefilm 12 may also be needed to protect the substrate 9 from the heatedconductive film 12.

The structure is annealed to cause crystallization of the active layerby application of the magnetic field as discussed above. When a dopedsilicon film is used as the conductive silicon layer 12, thecrystallization of the a-Si layer 11 is further sped up by seeding fromthe doped silicon layer 12, as was discussed earlier. The substrate mayalso be heated (for example, by furnace or by lamps) to aidcrystallization by the magnetic field. In this process, the entire a-Sifilm on a given substrate may be crystallized before any kind ofpatterns related to a TFT structure are formed. This is advantageoussince, at high enough furnace temperature, the substrate may shrink,affecting the spacing between TFT devices, if the patterns were alreadyformed before crystallization such as in the process of FIG. 2.Crystallization can be carried out in an inert ambient or an oxidizingambient. In embodiments where the conductive film 12 is above the activelayer 11, it may be etched away completely or can be left in the sourceand drain areas for contact purposes. In one embodiment, the undopedsilicon layer 11, and the doped silicon layer 12 (if present) arepreferably patterned into islands to isolate devices.

Subsequently, as shown in FIG. 3B, a gate insulator layer 13 and a gateelectrode layer are deposited. Since the gate electrode layer isconductive, the magnetic field crystallization process may be performedat this stage instead of at the earlier stage discussed above. In thiscase, if the furnace temperature during crystallization is high enough,the silicon island spacing may undesirably change. Also, since gateinsulator materials used in TFTs generally have low thermalconductivity, the efficiency of heating an a-Si layer by the gateelectrode would be low for a thick gate insulator layer.

In embodiments where the magnetic field crystallization process areperformed at this stage or later in the fabrication process, theconductive film 12 is unnecessary. The basic TFT structure is completedby patterning the gate electrode layer to form gate electrode patterns14, forming source-drain regions 15 by implantation of dopants into theundoped layer 11 (in embodiments where the doped layer 12 is entirelyetched from above the undoped layer or when the doped layer 12 is notused), depositing an interlayer dielectric layer (ILD) 16, forming holesthrough the interlayer dielectric layer 16 and gate insulator layer 13,and forming source and drain electrodes 17 by metal deposition andpatterning. Not all basic top gate coplanar TFT structure need an ILDlayer 16, but when such a TFT structure is used as a part of a TFT arrayfor display applications, an ILD layer may be needed to separate scanlines and data lines.

Some other applicable TFT structures that can be fabricated using thecrystallization methods of the present invention include, but are notlimited to, staggered TFTs and inverted co-planar TFTs. The staggeredTFT structure is a flipped structure of the inverted staggered structureshown in FIG. 2A, meaning that source-drain electrodes are close to thesubstrate while the gate electrode is on the top of the structure.

Application to Short Channel Devices

For use in system on panel (SOP) displays, the circuit-TFTs need to havehigh speed which requires the use of short channel devices. Forshort-channel devices, when the channel size is comparable to or shorterthan the poly silicon grain size, the TFT performance can be verynon-uniform, because the number of grain boundaries within a TFT channelcan vary from zero to one or even two. The crystallization methods ofthe present invention can be applied to precisely control the number ofgrain boundaries within a channel. This approach is described below.

An a-Si film is deposited as shown in FIG. 4. The areas on either sideof the channel are then doped by ion implantation or ion doping as shownin FIG. 4A or FIG. 4B or a doped gas phase amorphous silicon layer, or adoped microcrystalline silicon layer or any other conducting layer isformed on top of the a-Si film as shown in FIG. 4C. In the figures, 20represents conducting regions, while 21 represents undoped a-Si regions.

The conductive film may be above or below the a-Si film and it may be indirect contact with the a-Si film or be separated from the a-Si film byan intermediate layer. Upon applying the magnetic field, the dopedlayers or any other conducting layers are heated and begin tocrystallize the channel a-Si layer in thermal contact with them by heattransfer. The crystal grains grow laterally and meet in the middle ofthe two conducting regions, resulting only in one grain boundary per TFTin the direction perpendicular to the current flow. If no grain-boundaryperpendicular to the current is desired in a channel, the conductingregion must be used only on one side of the channel. The lateral crystalgrowth time depends upon the channel length. The crystallization thermalbudget can be further reduced if annealing is performed in an oxidizingambient at normal or higher pressure.

A second conducting layer 22 may also be used as shown in FIG. 4D to aidthe lateral crystallization process. The second conducting layer 22 maybe on the top or on the bottom, and may be in direct contact with thea-Si layer or may be separated by an intermediate layer (not shown). Itis particularly helpful to have region 20 in FIG. 4D be doped. The dopedfilms crystallize faster (especially boron doped films) and act as seedsfor lateral crystallization.

Although circuit TFTs require short-channel TFTs for obtaining highspeed as was mentioned above, pixel TFTs generally need longer channelsand both types of TFTs need to be formed on the same substrate at thesame reduced crystallization thermal budgets. When the above approach isused for crystallizing the active regions of a pixel TFT, the activeregion can not be fully crystallized as generally pixel-TFT channellengths are much longer than circuit-TFT channel lengths. The activeregions in the pixel-TFTs can be simultaneously crystallized with theactive regions in circuit-TFTs, if the channel areas of the pixel TFTsare completely covered by a conducting layer as in FIG. 1. Theconducting layer may be in direct contact with a-Si or be separated byan intermediate layer and may be above or below the a-Si layer. Anotheralternative is to divide the pixel-TFT channels into several shortchannels of the same lengths as those in the circuit TFTs as shown inFIGS. 5A, 5B and 5C. Upon annealing, the active regions in circuit-TFTsand pixel-TFTs are simultaneously crystallized. The number of grainboundaries perpendicular to current flow in the pixel-TFTs will be more,however since the pixel-TFT speed is not very important, the highernumber of grain boundaries in pixel TFTs is not a problem. Also, thenumber of grain boundaries per pixel TFTs would be same for all pixels,resulting in improved pixel to pixel uniformity. Such multi-channel TFTsalso have better reliability as applied voltage between source and drainis divided into several small biases.

Applications to Solar Cells

Polycrystalline silicon solar cells are devices which can also employthe crystallization techniques of the present invention duringfabrication.

FIG. 6 shows a cross-sectional schematic of a p-i-n type of solar cellor a photosensor. A transparent conductor 62 is deposited on atransparent substrate 61. In one embodiment, the transparent conductor62 is indium tin oxide (ITO). The transparent substrate 61 is asubstrate which can allow incident light such as solar radiation to passthrough it. In one embodiment, the transparent substrate is glass. Thetransparent conductor 62 is termed the bottom electrode 62 herein. Ap-type amorphous silicon or p-type microcrystalline silicon layer 63 isthen deposited. The thickness of this layer 63, which also serves as awindow to incoming radiation, would be preferably limited to severalhundred angstroms, as thicker films will reduce the intensity ofincoming radiation from reaching the intrinsic layer which isresponsible for creating solar power. An intrinsic silicon (preferablyan amorphous silicon layer) 64 is deposited on top of the p-type layer63. This film is preferably several thousand angstroms to severalmicrons thick.

An n-type amorphous or n-type microcrystalline silicon layer 65 isdeposited on top of the intrinsic silicon layer 64. A top electrode 66,which is made from a material including, but not limited to, metal, isdeposited. All the silicon (p-type, n-type and intrinsic) films may becrystallized by heating caused by a magnetic field using the methods ofthe present invention described herein. Heating by the magnetic field ismore efficient due to the presence of conductor films in the structure,such as doped silicon films and the top and bottom electrode films.Additional heating may be supplied by heating the substrate in aresistively heated furnace or by lamps. If metal contamination is anissue, the heating can be done before the top electrode 66 is deposited.If a transparent electrode such as ITO can not be used as the bottomelectrode 62 due to the possibility of heating damage to the transparentelectrode during the crystallization process, a non-transparentelectrode such as metal can be used as the bottom electrode 62. However,to allow the incident light to pass through, such an electrode must bepatterned into grids or a transparent electrode can be formed on top andlight can be incident from the top. In the current structure, the p-typesilicon layer 63 is below the intrinsic silicon layer 64 and the n-typelayer 65 is above the intrinsic silicon layer. However, it is alsopossible to use n-type silicon below the intrinsic silicon layer andp-type silicon above the intrinsic silicon layer.

Other structures where the above method may be applied include, but arenot limited to, P-N junction solar cells and shotckey diode solar cellsor photosensors. The P-N junction solar cell is similar to a P-I-N solarcell, except that there is no intrinsic layer (i-layer). The shotckeystructures are preferably PI or NI structures, where P is p-typesilicon, N is N-type silicon and I is intrinsic silicon. All thesestructures would need top and bottom electrodes for the currenttransport.

Accordingly, it is to be understood that the embodiments of theinvention herein described are merely illustrative of the application ofthe principles of the invention. Reference herein to details of theillustrated embodiments is not intended to limit the scope of theclaims, which themselves recite those features regarded as essential tothe invention.

1. A method of crystallizing an undoped or a lightly doped amorphoussilicon (a-Si) film comprising the steps of: a) forming a stackedstructure of the a-Si film and a conductive film; and b) subjecting thestacked structure to a varying or an alternating magnetic field to heatthe stacked structure to cause a crystallization of the a-Si film byheat transfer from the conductive film to the a-Si film.
 2. The methodof claim 1, wherein step a) comprises the substep of forming anintermediate layer between the a-Si film and the conductive film.
 3. Themethod of claim 1, wherein crystallization of the a-Si film is aided byadditional heating by a heating apparatus selected from the groupconsisting of a furnace, a lamp or a light source, and a combination ofa furnace and a lamp or light source.
 4. The method of claim 1, whereinthe conductive film is formed continuously or discontinuously above,below, or both above and below the a-Si film.
 5. The method of claim 1,wherein the conductive film has a conductivity of at least 10⁻³ S/cm. 6.The method of claim 1, wherein the conductive film comprises at leastone layer selected from the group consisting of: a) a p-type dopedamorphous silicon layer; b) a p-type doped microcrystalline siliconelayer; c) an n-type doped amorphous silicon layer; d) an n-type dopedmicrocrystalline silicon layer; e) a metal layer; f) a graphite layer;g) a layer made of magnetic material; h) a transparent conductor layer;i) a layer comprising Fe; j) a composite layer comprising at least onematerial from a) through i); and k) any combination of a) through j). 7.The method of claim 1, wherein the conductive film comprises at leastone doped silicon layer formed by deposition by flowing dopantcontaining gases with silicon forming gases.
 8. The method of claim 1,wherein the conductive film comprises at least one doped silicon layerformed by implanting dopant atoms into the a-Si film.
 9. The method ofclaim 1, wherein the conductive film comprises at least one dopedsilicon layer doped with at least one dopant selected from the groupconsisting of: a) B; b) P; c) As; d) Sb; e) In; f) Ga; g) Al; and h) anycombination of a) through g).
 10. The method of claim 1, wherein theconductive film comprises at least one doped silicon layer having adopant concentration of at least 10¹⁸ cm⁻³.
 11. The method of claim 1,wherein the conductive film comprises at least one doped silicon layerhaving a dopant concentration of at least 10²⁰ cm⁻³.
 12. The method ofclaim 1, wherein the intermediate layer comprises at least one layerselected from the group consisting of: a) at least one layer containingsilicon oxide; b) at least one layer containing silicon nitride; and c)a combination of a) and b).
 13. The method of claim 1, wherein athickness of the conductive film is between 50 angstroms and 5000angstroms.
 14. The method of claim 1, wherein a thickness of theintermediate layer is between 10 angstroms and 5000 angstroms.
 15. Themethod of claim 1, wherein an oxidizing ambient is used during thecrystallization process.
 16. The method of claim 1, whereincrystallization is carried out at an ambient at a pressure higher than 1atmosphere.
 17. A method of forming a TFT structure having a channel, asource, a drain and a gate, comprising the steps of: a) forming at leastone gate electrode pattern on a substrate; b) depositing a gateinsulator layer and an active layer of a-Si sequentially; c) subjectingthe structure to a varying or an alternating magnetic field to causecrystallization of the active layer; d) forming a doped layer ofsilicon, either continuously or discontinuously; e) patterning the dopedlayer and the active layer to form islands to isolate devices; f)depositing at least one source-drain electrode film; g) patterning thesource-drain electrode film to form at least one source-drain pattern;and h) etching the doped layer from above the active layer.
 18. Themethod of claim 17, wherein steps a) through h) are performedsequentially, except that step c) is performed at a time selected fromthe group consisting of: a) after step d); b) after step e); c) afterstep f); d) after step g); and e) after step h).
 19. The method of claim17, wherein crystallization of the active layer is aided by additionalheating by a heating apparatus selected from the group consisting of afurnace, a lamp or a light source, and a combination of a furnace and alamp or light source.
 20. The method of claim 17, wherein a conductivityof the doped layer of silicon is at least 10⁻³ S/cm.
 21. The method ofclaim 17, wherein the doped layer of silicon has a doping concentrationof at least 10¹⁸ cm⁻³.
 22. The method of claim 17, wherein the dopedlayer of silicon has a doping concentration of at least 10²⁰ cm⁻³. 23.The method of claim 17, wherein the doped layer of silicon is doped withat least one dopant selected from group consisting of: a) B; b) P; c)As; d) Sb; e) In; f) Ga; g) Al; and h) any combination of a) through g).24. The method of claim 17, wherein an oxidizing ambient is used duringthe crystallization process.
 25. A method of fabricating a coplanar topgate TFT structure having a channel, a source, a drain, and a gatecomprising the steps of: a) forming an active layer of a-Si on asubstrate; b) forming a conductive layer on the active layer of a-Si; c)subjecting the structure to a varying magnetic field or an alternatingmagnetic field to heat the conductive layer to crystallize the activelayer of a-Si by heat transfer from the conductive layer to the activelayer; d) removing the conductive layer; e) patterning the active layerto form islands to isolate devices; f) forming a gate insulator layer;g) depositing a gate electrode layer and forming at least one gateelectrode pattern; h) doping at least one source region and at least onedrain region; and i) depositing a source and drain electrode layer, andforming at least one source and drain electrode pattern.
 26. The methodof claim 25, further comprising, before step a), the steps of: j)forming a continuous or patterned conductive film on the substrate,wherein the conductive film is either transparent or non-transparent;and k) forming a barrier layer on the conductive film; wherein, in stepa), the a-Si layer is formed on the barrier layer.
 27. The method ofclaim 25, wherein the conductive film comprises at least one dopedsilicon layer having a dopant concentration of at least 10¹⁸ cm⁻³. 28.The method of claim 25, wherein the conductive film comprises at leastone doped silicon layer having a dopant concentration of at least 10²⁰cm⁻³.
 29. The method of claim 25, further comprising the step of formingan intermediate layer between the active layer and the conductive layer.30. The method of claim 25, wherein crystallization of the active layerof a-Si is aided by additional heating by a heating apparatus selectedfrom the group consisting of a furnace, a lamp or a light source, and acombination of a furnace and a lamp or light source.
 31. The method ofclaim 25, wherein crystallization of the active layer of a-Si isperformed in the presence of an oxidizing ambient.
 32. The method ofclaim 25, further comprising the step of forming a patterned inter-layerdielectric layer between steps h) and i).
 33. A method of fabricating acoplanar top gate TFT structure having a channel, a source, a drain, anda gate comprising the steps of: a) forming an active layer of a-Si on asubstrate; b) patterning the active layer to form islands to isolatedevices; c) forming a gate insulator layer; d) depositing a gateelectrode layer; e) subjecting the structure to a varying magnetic fieldor an alternating magnetic field to heat the structure to causecrystallization of the active a-Si layer; f) patterning the gateelectrode layer to form at least one gate electrode pattern; g) dopingat least one source and drain region; h) depositing a source and drainelectrode layer; and i) forming at least one source and drain electrodepattern.
 34. The method of claim 33, further comprising, before step a),the steps of: j) forming a continuous or patterned conductive film onthe substrate, wherein the conductive film is either transparent ornon-transparent; and k) forming a barrier layer on the conductive film;wherein, in step a), the a-Si layer is formed on the barrier layer. 35.The method of claim 33, wherein crystallization of the active layer isaided by additional heating by a heating apparatus selected from thegroup consisting of a furnace, a lamp or a light source, and acombination of a furnace and a lamp or light source.
 36. The method ofclaim 33, wherein step e) is carried out after doping of source anddrain regions in step g) or after any process step subsequent to stepg).
 37. The method of claim 33, further comprising the step of forming apatterned inter-layer dielectric layer between steps g) and h).
 38. Amethod of fabricating a staggered TFT structure having a channel, asource, a drain, and a gate comprising the steps of: a) forming at leastone source and drain electrode pattern on a substrate; b) forming anactive layer of a-Si comprising at least one channel region and at leastone doped source drain pattern on either side of the channel region; c)patterning the active layer to form at least one island to isolatedevices; d) forming a gate insulator layer; e) depositing a gateelectrode layer; f) subjecting the structure to a varying magnetic fieldor an alternating magnetic field to heat the structure and crystallizethe active layer; and g) patterning the gate electrode layer to form atleast one gate electrode pattern.
 39. The method of claim 38, whereincrystallization of the active layer is aided by additional heating by aheating apparatus selected from the group consisting of a furnace, alamp or a light source, and a combination of a furnace and a lamp orlight source.
 40. A method of forming a crystalline silicon thin filmsolar cell comprising the steps of: a) forming a first electrode on asubstrate; b) sequentially depositing at least two layers selected fromthe group consisting of: i) at least one p-type silicon layer (P); ii)at least one intrinsic amorphous silicon (a-Si) layer (I); iii) at leastone n-type silicon layer (N); and iv) any combination of i) throughiii); c) forming a second electrode; and d) subjecting the structure toa varying magnetic field or an alternating magnetic field to crystallizethe amorphous silicon layer.
 41. The method of claim 40, whereincrystallization of the a-Si layer is aided by additional heating by aheating apparatus selected from the group consisting of a furnace, alamp or a light source, and a combination of a furnace and a lamp orlight source.
 42. The method of claim 40, wherein at least one of thefirst electrode or the second electrode is formed using a transparentconductor material.
 43. The method of claim 40, wherein the p-typesilicon layer and the n-type silicon layer each have an amorphousstructure or a microcrystalline structure.
 44. The method of claim 40,wherein, in step b), the formed structure is selected from the groupconsisting of: a) PIN; b) NIP; c) NI; d) IN; e) PI; f) IP; and g) anycombination of a) through f).
 45. A method of crystallizing an a-Silayer comprising the steps of: a) forming a structure having a stack ofthe a-Si layer and a plurality of discontinuous areas of a firstconducting layer or a structure with a plurality of discontinuousconducting regions within the a-Si layer, where the first conductinglayer is either directly in contact with the a-Si or the firstconducting layer is separated from the a-Si layer by an intermediatelayer; and b) subjecting the structure to a varying magnetic field or analternating magnetic field to heat the first conducting layer orconducting regions to cause crystallization of the a-Si layer by lateralcrystal growth in the a-Si layer starting from discontinuous areas ofthe first conducting layer or the conducting regions.
 46. The method ofclaim 45, wherein crystallization of the a-Si layer is aided byadditional heating by a heating apparatus selected from the groupconsisting of a furnace, a lamp or a light source, and a combination ofa furnace and a lamp or light source.
 47. The method of claim 45,wherein a second conducting layer is continuously formed over or underthe structure formed in step a), wherein the second conducting layer isin contact with the structure formed in step a) or it is separated fromthe structure formed in step a) by an intermediate layer.
 48. The methodof claim 45, wherein step b) is carried out in the presence of anoxidizing ambient.
 49. A method of fabricating a coplanar top gate TFTstructure having a channel, a source, a drain, and a gate comprising thesteps of: a) forming a continuous or patterned conductive film on asubstrate, wherein the conductive film is either transparent ornon-transparent; b) forming a barrier layer on the conductive film; c)forming an active layer of a-Si on the barrier layer; d) subjecting thestructure to a varying magnetic field or an alternating magnetic fieldto heat the conductive layer to crystallize the active layer of a-Si byheat transfer from the conductive layer to the active layer; e)patterning the active layer to form islands to isolate devices; f)forming a gate insulator layer; g) depositing a gate electrode layer andforming at least one gate electrode pattern; h) doping at least onesource region and at least one drain region; and i) depositing a sourceand drain electrode layer, and forming at least one source and drainelectrode pattern.
 50. The method of claim 49, wherein the conductivefilm is a continuous, unpatterned film comprising a transparentconductor.
 51. The method of claim 49, wherein crystallization of thea-Si layer is aided by additional heating by a heating apparatusselected from the group consisting of a furnace, a lamp or a lightsource, and a combination of a furnace and a lamp or light source.